1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to interconnect structures for connecting different device levels by vias extending through the substrate material of the devices.
2. Description of the Related Art
In modem integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are continuously decreased with the introduction of every new circuit generation to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although transistor elements are the dominant circuit element in highly complex integrated circuits which substantially determine the overall performance of these devices, other components such as capacitors and resistors, and in particular a complex interconnect system or metallization system, may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area.
Typically, as the number of circuit elements, such as transistors and the like, per unit area may increase in the device level of a corresponding semiconductor device, the number of electrical connections associated with the circuit elements in the device level may also be increased, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines, providing the inner-level electrical connection, and vias, providing the intra-level connections, may be formed on the basis of highly conductive metals, such as copper and the like, in combination with appropriate dielectric materials to reduce the parasitic RC (resistive capacitive) time constants, since, in sophisticated semiconductor devices, typically, signal propagation delay may substantially be restricted by a metallization system rather than the transistor elements in the device level. However, expanding the metallization system in the height dimension to provide the desired density of interconnect structures may be restricted by the parasitic RC time constants and the effects imposed by the material characteristics of sophisticated low-k dielectrics. That is, typically, a reduced dielectric constant is associated with reduced mechanical stability of these dielectric materials, thereby also restricting the number of metallization layers that may be stacked on top of each other in view of yield losses during the various fabrication steps and the reduced reliability during operation of the semiconductor device. Thus, the complexity of semiconductor devices provided in a single semiconductor chip may be restricted by the capabilities of the corresponding metallization system and in particular by the characteristics of sophisticated low-k dielectric materials, since the number of metallization layers may not be arbitrarily increased. For this reason, it has also been proposed to further enhance the overall density of circuit elements for a given size or area of a respective package by stacking two or more individual semiconductor chips, which may be fabricated in an independent manner, however, with a correlated design to provide in total a complex system while avoiding many of the problems encountered during the fabrication process for extremely complex semiconductor devices on a single chip. For example, appropriately selected functional units, such as memory areas and the like, may be formed on a single chip in accordance with well-established manufacturing techniques including the fabrication of a corresponding metallization system, while other functional units, such as a fast and powerful logic circuitry, may be formed independently as a separate chip wherein, however, respective interconnect systems may enable a subsequent stacking and attaching of the individual chips to form an overall functional circuit, which may then be packaged as a single unit. Thus, a corresponding three-dimensional configuration may provide increased density of circuit elements and metallization features with respect to a given area of a package, since a significant larger amount of the available volume in a package may be used by stacking individual semiconductor chips. Although this technique represents a promising approach for enhancing packing density and functionality for a given package size for a given technology standard while avoiding extremely critical manufacturing techniques, for instance in view of stacking a large number of highly critical metallization layers, appropriate contact elements may have to be provided to enable the electrical connections of the individual semiconductor chips in a reliable and well-performing manner. To this end, it has been suggested to form through hole vias through the substrate material of at least one of the chips to enable electrical contact to respective contact elements of a second semiconductor chip, while the metallization system of the first semiconductor chip may further be available for connecting to other semiconductor chips or a package substrate and the like. These through hole vias may typically represent contact elements of a high aspect ratio, since the lateral dimensions of these vias may also be reduced in view of saving valuable chip area, while, on the other hand, the thickness of the substrate material may not be arbitrarily reduced. Additionally, in view of electrical performance, the conductivity of the through hole vias should be maintained at a high level to accommodate the required high current densities and also reduce signal propagation delay in systems in which exchange of electrical signals between individual semiconductor chips may have to be accomplished on the basis of moderately high clock frequencies.
In view of this situation, in conventional approaches, the corresponding high aspect ratio through hole vias may be formed on the basis of well-established manufacturing techniques also known from the fabrication of contact structures and metallization systems, which may involve the etching of respective openings, such as via openings and trenches, in a moderately thin dielectric material and the subsequent filling of these openings with metal-containing materials, such as copper in combination with conductive barrier materials, such as titanium nitride, tungsten and the like. By transferring corresponding technology to a fabrication sequence for through hole vias, appropriate high conductivity values may be obtained in conformity with requirements with respect to enhanced electrical performance. However, since the temperature stability of these materials may be inferior, typically these process steps may have to be performed at a very advanced manufacturing stage, i.e., after any high temperature processes that may usually be required during the formation of circuit elements, such as transistors, in the device level. Thus, the manufacturing steps involved in forming the high aspect ratio openings for the through hole vias and the subsequent filling in of a highly conductive material may significantly affect the overall process flow and may have an adverse influence on the circuit elements in the device level. For example, sophisticated etch and masking regimes may have to be used to etch through the substrate, which may thus also affect any circuit element that may have already been formed in the device level at this manufacturing stage.
On the other hand, conductive materials exhibiting a moderately high temperature stability, such as doped polysilicon, may exhibit an inferior conductivity so that forming the corresponding through hole vias at an early manufacturing stage on the basis of temperature stable polysilicon material may be less than desirable in view of electrical performance of the resulting interconnect structure.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.